DesignCon 2009: Paper Awards

From: Subject: DesignCon 2009: Paper Awards Date: Thu, 14 Jan 2010 19:21:38 -0500 MIME-Version: 1.0 Content-Type: multipart/related; type="text/html"; boundary="----=_NextPart_000_0000_01CA954E.CB2F1A90" X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.5579 This is a multi-part message in MIME format. ------=_NextPart_000_0000_01CA954E.CB2F1A90 Content-Type: text/html; charset="windows-1256" Content-Transfer-Encoding: quoted-printable Content-Location: http://www.designcon.com/2009/paperawards/index.asp DesignCon 2009: Paper Awards

Paper Awards

=20 Congratulations to the DesignCon Paper Award=20 Winners!

DesignCon Paper Awards recognize contributions to the = educational=20 goals of the DesignCon program. Papers are judged both on = the merits=20 of the written document and on the quality of their = presentation at=20 DesignCon 2009.

Chip-Level Design Category:

1-WA2 | Desi= gn=20 Space Exploration for High Performance Signal Processing = Hardware=20 using ESL Design Methodologies

Nitin Chawla, Senior Member of Technical = Staff,=20 STMicrolelctronics PvT
Pierre Busson, = Advanced=20 Architect Expert, STMicrolelctronics PvT
Thierry=20 Michel, HW Staff Engineer, STMicrolelctronics=20 PvT
Gagan Midha, Senior Design Engineer, = STMicrolelctronics PvT
Harvinder Singh, = Technical Specialist, STMicrolelctronics PvT =
Pascal=20 Urard, Director System Methods, STMicrolelctronics = PvT

3-TA4 | Towa= rd=20 Harnessing the True Potential of IP Reuse

Kathryn Kranen, Chief Executive Officer, = Jasper=20 Design Automation
Homayoon Akhiani, = Principal=20 Engineer, Jasper Design Automation
Yann=20 Antonioli, Program Director, Jasper Design=20 Automation
Craig Deaton, Principal = Methodology=20 Engineer, Jasper Design Automation
Norris Ip,=20 Director, Engineering, Jasper Design=20 Automation
Lawrence Loh, Director, = Application=20 Engineering, Jasper Design Automation
Rajeev=20 Ranjan, Chief Technology Officer, Jasper Design = Automation=20

Board and System Design = Category:

4-WP1 | SSO = Noise, Eye Margin, and Jitter Characterization for I/O Power = Integrity

Vishram Pandit, Senior Analog Engineer,=20 Intel
Myoung Choi, Design Engineer,=20 Intel
Hsiao-ching Chuang,=20 Intel
Ashish Pardiwala, Design Engineer, = Intel
Ruhul Quddus, Intel

5-TP2 | A=20 Simple Via Experiment

Michael Steinberger, Distinguished = Member of=20 Technical Staff, Signal Integrity = Software
Stephen=20 Scearce, High Speed Design Group Manager, Cisco=20 Systems
Douglas White, High Speed Design = Specialist, Cisco Systems

Interconnect Design Category:

7-TA2 | Prac= tical=20 Analysis of Backplane Vias for 5 Gbps and = Above

Eric Bogatin, President, Bogatin=20 Enterprises
Sanjeev Gupta, Signal = Integrity=20 Specialist, Agilent
Mike Resso, Signal = Integrity=20 Measurement Specialist, Component Test Division,=20 Agilent
Bert Simonovich, Signal = Integrity and=20 Backplane Architecture, Nortel

7-TH2 | New = Serial Link Simulation Process, 6 Gbps SAS Case=20 Study

Donald Telian, SI = Consultant
Ravinder=20 Ajmani, Senior Engineer, Hitachi = GST
Kent=20 Dramstad, Applications Engineer, IBM =
Adge=20 Hawes, Development Architect, IBM
Paul=20 Larson, Senior Engineer, Hitachi GST

High-Speed and RF Design = Category:

9-WP2 | 40/1= 00=20 Gbps Transmission Over Copper: Myths and = Realities

Ali Enteshari, Ph.D. Candidate, Center = for=20 Information and Communications Technology Research, The = Pennsylvania=20 State University
Mohsen Kavehrad, = Professor, The=20 Pennsylvania State University

11-WP2 |EMI= =20 from Multi-Gigabit SerDes Differential = Pairs

Philippe Sochoux, EMC Design Manager, = Central=20 Engineering, Cisco Systems
Alpesh Bhobe, = EMC=20 Design Engineer, Cisco Systems
Jinghan = Yu, EMC=20 Design Engineer, Cisco Systems
Morris = Hsu,=20 Intern, Cisco Systems Morris Hsu, Intern, Cisco Systems

Power Integrity and Power-Award = Design=20 Category:

10-WA3 |=20 Examining the Impact of Split Planes on Signal and Power=20 Integrity

Jason Miller, Senior Staff Engineer, Sun = Microsystems
Gustavo Blando, Signal = Integrity=20 Staff Engineer, Sun Microsystems
Roger = Dame,=20 Senior Staff Engineer, Sun Microsystems
K. Barry = A.=20 Williams, Principal Engineer, Sun=20 Microsystems
Istvan Novak, Distinguished = Engineer, SPARC Volume Servers, Sun Microsystems

Test and Measurement = Category:

12-WA1 | Mea= surement-Assisted=20 Electromagnetic Extraction of Interconnect Parameters on = Low-Cost=20 FR-4 boards for 6-20 Gbps Applications

Yuriy Shlepnev, President,=20 Simberian
Alfred Neves, Senior Staff = Signal=20 Integrity Engineer, Teraspeed Consulting Group =
Tom=20 Dagostino, Vice President Engineering, Teraspeed=20 Labs
Scott McMorrow, President, = Teraspeed=20 Consulting

Attendees:

Event=20 Overview=20
Schedule=20
Exhibi= ts=20 PLUS=20
Exh= ibitor=20 List and Floor Plan=20
Busin= ess=20 Forum=20
Technical=20 Program Committee=20
Sponsors=20
FAQ=20
Register=20
Contact=20 Us

Exhibitors:

2009=20 Prospectus=20
Exh= ibitor=20 List and Floor Plan=20
Exhibi= t=20 Space Contract=20
Spo= nsorship=20 Opportunities PDF=20
Sponsorship=20 Contract PDF
Ex= hibitor=20 Manual PDF=20
Logo=20 Library
PR= =20 Opportunities

Authors:

Information for=20 Speakers=20
Speaker/A= uthor=20 Registration
Speaker=20 Marketing Opportunities

Press:

PR = Contact=20
Press=20 Releases=20
On-Line=20 Media Center=20
Press=20 Registration=20

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